So as promised I spent a bit of the bank holiday weekend hacking on the FPGA Spectrum to fix a few bugs. In the end I got carried away and finished up with a full implementation of the 128K Spectrum +2A running ResiDOS and loading emulator images from an SD card. It’s still not cycle accurate, but it is feature complete apart from the disk controller, which isn’t really needed thanks to the ZXMMC+ compatibility that went in as well.
Emulating bus contention and improving the cycle accuracy of the T80 core is definitely on the cards, but for now the ability to finally load emulator images from SD makes the machine extremely usable. An explanation of how to get this up and running is a job for another post (hint: format the card as IDEDOS and bootstrap ResiDOS into the extra RAM), but for the time being here is a detailed write-up and the full VHDL source.
And let’s not forgot the obligatory eye candy…
As promised, some more detailed design notes for my BBC B design are now available.
Planning to revisit the Spectrum design next for some bug fixes, as it is clear there is still quite a bit of interest in that.
I added a video of the FPGA BBC in action, shot straight off the TV.
You can see the MMBEEB ROM extensions providing access to multiple disk images on the SD card, then some messing about on Chuckie Egg and Boffin.
BBC Micro boot screen running on FPGA
It’s been a while since the Spectrum project and, although there is still work left to do on that, I eventually gave in and did another great British computer from my childhood – the BBC B. Getting this machine up and running has been an interesting job given its complexity. For something that first came out in 1981 it really is a sophisticated computer, and one that I’m sure anyone who grew up in the UK in the 80’s and early 90’s will remember.
I’ve written this one up on its own page so that it doesn’t disappear, and the Speccy will get the same treatment in the next few weeks. A bitstream image is provided for you to run on your own DE1 board, if you have one, and the full VHDL source code is available too.
A detailed description of the design is also in the works, and should be ready in a day or two.
Sorry it took so long, but I’ve finally cleaned up the source code ready for publishing, and here it is. This contains a Quartus project file, so it should load and compile straight away. I used Quartus 9.1 Web Edition, available from the Altera website. There is also a pre-compiled .sof image which should work straight away if you have a DE1.
A full write-up will follow, but here is a quick summary:
Last week I was made aware of this post on RS DesignSpark about a project, currently in the very early planning stage, to build a Sinclair Spectrum on an FPGA. As it happens I have a similar project well under way, and I have promised to write it up…
Several years ago I implemented most of the ULA in VHDL on a MAX7000 CPLD, mainly as an exercise to brush up on my HDL. I didn’t have enough space to fit the keyboard interface so it was pretty useless, but it did boot! The complete system used a pair of SRAMs, real Z80 and the Sinclair ROM in flash.
Back at the beginning of this year I decided to brush up on my HDL again and I bought myself an Altera DE1 development kit. The heart of this board is a Cyclone II FPGA with a range of support hardware including 512KB SRAM, 8MB SDRAM, 4MB flash, an I2S audio codec, VGA port and the usual switches, LEDs and buttons. I would highly recommend it for anyone looking for a relatively cheap way to play with FPGAs.
I had a dead motherboard that had been kicking around for a while after a failed BIOS update. The flash part on there was the Winbond W39V040B, which is 3.3V only and has an LPC interface. The device programmer I have access to wouldn’t touch it, so I put together some simple AVR code to handle the protocol and connected the device up to my STK500. Although reading the device posed no problems, it quickly became apparent that the flash chip was not responding properly to write transactions. This meant there was no way to erase or program it, and is presumably why the BIOS flash failed in the first place.
Searching through the junk box I managed to find a dual-mode LPC/FWH device of the same size (PMC Pm49FL004). This one was responding properly to write commands, but I needed a way of reliably transferring the new BIOS image down to the AVR. Continue reading
AVR32 NGW100 Driving an STN LCD Module
I’ve had a few controllerless QVGA (320×240) mono LCD modules lying around for a while looking for some use. These are fairly easy to get going with a low-end microcontroller using an external controller IC like the SED1335, but that’s another story. I’d been thinking about doing some sort of integrated home automation project, and since this would need a user interface and I happened to have an NGW100 going spare, getting one of these displays to run on the AP7000’s integrated LCD controller seemed like a nice idea.
The NGW100 only has a 16-bit interface to its already relatively slow DRAM, so driving a high-res colour LCD from it leads to a fairly obvious slowdown. For this application a mono display would be adequate, and easier to drive, requiring only a 4-bit data bus, the 3 clocks and a GPIO to power up the drivers. The LCDC has no problem driving an STN panel, although I had to deviate from the datasheet in one area to get it to work – more on that later.