Quite a bit of work has been going on behind the scenes on the FPGA based accelerator card, so it’s time for an update. TG68 is now running stable in 68020 mode at a clock frequency of 6x the motherboard clock (about 42 MHz), and an instruction cache has been implemented that can feed the core with 0 tick latency in the event of a cache hit. This has added up to some pretty impressive performance, with AIBB’s integer maths test running at more than double the speed of a 25 MHz 68040 A4000.
Being reasonably content with performance, and expecting a further increase on the final hardware anyway due to the use of a faster FPGA, we moved on to one of the other key features that this board will have at launch – support for booting from the on-board micro SD.
The interface is a full 4-bit SDIO controller that can theoretically support UHS-I speeds with suitable voltage switching, although it is currently running much more slowly due to the long wiring on the prototype. The controller block is designed so that it can be mapped into the Amiga’s address space (and I already showed off some pics of card initialisation from AMOS using this method), but to enable it to boot on an unmodified Kickstart an alternate mode allows it to emulate an IDE drive. The addition of the key parts of Gayle allow the A500 running Kickstart 2.05 or higher to boot directly from an RDB formatted SD card with no special drivers.
Performance is currently reduced significantly due to missing multiple block support in the IDE emulation, but around about 1MB/s is still achievable with most cards and the missing support is next on my list to add. The bottleneck is mainly due to the single-block access time of the card rather than any transfer rate issue.
As well as the bootable Gayle IDE emulation the intention is to retain the low-level memory mapped access to the SD controller and to allow it to act as a DMA master. Although taking advantage of this mode would require a custom device driver it would have the potential to speed things up dramatically.
On the latest build WhichAmiga now identifies the machine as an A600 (because of the fake Gayle), and detects the CPU as a 68020 running at 85.2 MHz (interestingly, double the actual clock speed). Booting to a simple Workbench installation takes just a few seconds, and the “full” version of Classic Workbench is up and running in about 15 seconds from letting go of reset. All of this is being run on an A500+ board with Kickstart 3.1 in the motherboard socket. A 1MB chip RAM expansion is fitted in the trapdoor slot bringing the total memory up to 2 MB chip and 32 MB fast on the accelerator.
Please port this to the X68000. There are no good accelerators available for that platform and the Amiga has a bajillion (it’s a real number the InterNet told me so).
It’s quite portable, but the X68000 looks as rare as hens’ teeth!
Any plans on publishing the fixes to TG68?
There are none. TG68 is unmodified in the current version.
Love the work you have done, this was something I wanted to get started with at some point, cheap, fast and hackable accelerators and more.
The use of a cheap FPGA board could be interesting as you would only need to add the bits and bobs that were missing like the 3,3v5v conversion and things like SD card adapters and ram.
Any idea what kind of FPGA you are going to use in the next version?
Is there room to add an HDMI connector?, maybe to ad an RTG or emulate the normal video out?
Any news?,
Development has been held up a bit due to the business impact of the current situation, but the production hardware design is quite close to completion and I will be releasing some renders and a list of features soon.
Yes, C….. has been tough for a lot of people, it has played havoc on my life also.
Good to hear that the project is still live and kicking.
Why don’t you have a rom inside an eeprom onboard?, you could also use it for settings and stuf, it would speed up everything from the get go and you could skip the Gayle stuff. (it would be a little bit less compatible probably)
How about throwing in some SPIs, so we can add network (I think you already did a driver for a cheap device), a DAC (AHI driver needed!?), maybe even a DSP?
How much RAM are you planing for the final PCB? You aren‘t bound to the RAM of the DE0 anymore then, so what will it be? 64MB? 128? 😀
RTG would be nice, but it blows things out of proportion, I think. I mean you‘d need HDMI output, but then regular Denise output will necessitate manual switching if not even a second monitor. Then sound… yes, HDMI could use an AHI driver, but what about Paula sound then? Too much a hassle and will make the project a lot more expensive, I guess. Maybe another connector for a future add-on?
All good ideas. Work is progressing well again now after a couple of months’ delay, and I will be showing it off soon once it is ready for production. I don’t think you will be disappointed!
Sweet! chances this could go on a 3000/4000 CPU card? Also speak to Chucky about rolling it into the reamiga 1200 board, soldering a 68ec020 on seems wrong when this is available!
Thinking about a CPU card version yes. The 1200 version will come first to prove out the 32-bit bus because I have a 1200 to test it in. The BGA components might be an obstacle for including it on Chucky’s board or similar, but a module might be an option.
For rev vx.0 something like the RBpi compute card format would be nice?
That way you could use a dumb adapter to fit it to the machine you like.
A few extra GPIO’s for future expansions…..
Nice….
What a great development! May I suggest testing it with the A1200+ by Jeroen Vandezande. It has no CPU, so you are forced to use an accelerator like yours 🙂
https://bitbucket.org/jvandezande/amiga-1200/src/master/
Any news on this?
No updates on the SD feature specifically, but I posted an update about manufacturing on the EAB thread the other day.
If you have to delay getting the final board fabricated could you at least release VHDL for the DE0 Nano board, even without SPI and SD card code?
I’d like to see how the memory control and other stuff is implemented, I’m trying to learn how to read and write HDL.
I could cobble together a level converter board and have fun with a fast A500 😀
Having this as a bridge board for the DE0 Nano with the usual and simple IDE port would also be a great product (maybe additional 32MB RAM on the bridge, probably unnessesary), should be cheaper and faster to make than the whole deal with FPGA on board.
First.. Nice work. quite interesting. very much appreciated.
Any accelerator board for the Amiga line are welcome in the retro community and soft-cores are a nice way to go these days I think.
In Europe there are a quite large community of Amiga users, many of them getting their hands on more than one accelerator board for their machines.
I myself are from Sweden and a bit of “collector” myself and I know several people that have 4-8 different boards and also more than one Amiga.
The A3000 and A4000 need alternatives as well as the A500 and A1200 models. CD TV have been up but are a bit harder to create boards for I think.
When the speed of a 68000 core goes beyond a 68060 at 80Mhz or closing in on the retro accelerator boards, things get really interesting. If implementation of MMU and FPU also gets in to play, then the Amiga will have passed a milestone. One goal for the future would be a softcore that runs at 100Mhz + and have MMU and FPU and perhaps a developed set of 68060 instructions to the core.
All development are good for the quite large Amiga community and nice projects like yours have a lot of eyes following the project.
With Hyperion releasing their os 3.2 update the Amiga line got an “vitamin injection” not long ago and the interest are growing as we speak.
The Amiga line also have a unique history and truly are the computer that would not die. People like you are a piece of this unique history of the Amiga and that are much appreciated.