The Amiga is still a popular platform with enthusiasts, with the vibrant add-on scene still seeing new accelerator cards being developed. Most of these are based on the long obsolete faster derivatives of the 68000, such as the 68030 and 68060. These are getting increasingly hard to find for a reasonable price.
For the last few weeks I’ve been tinkering with hooking an FPGA up to an A500+ in place of its 68000 CPU with a view to using the open-source TG68 core as a fast 68020. This core is already proven in projects such as Minimig and MISTer, so it seemed like a logical choice. Rather than going straight to a custom PCB I made the decision to use an existing FPGA development board that I had on hand, along with a simple level shifting interface put together on stripboard. This has proved to work perfectly well for testing, although the grounding did need to be beefed up with copper tape to get things working reliably. A proper PCB with an FPGA integrated will be designed in due course.
The FPGA board itself is a Terasic DE0 Nano, for no particular reason other than I had a spare one. This features an Intel Cyclone IV FPGA as well as 32MB of SDRAM and a few other peripherals that aren’t of much interest here.
The TG68 does not have a regular 68000 interface, nor does it implement a real 68000 bus cycle. The Amiga is extremely sensitive to the timing of the motherboard bus cycle due to the way that Agnus handles its DMA cycles to chip memory. Getting the motherboard bridge logic properly synchronised was one of the hardest aspects of the design so far. To make it work reliably the accelerator needs to run at an even multiple of the motherboard clock – 42.6MHz currently. This may not seem like a huge step up, but TG68 typically executes a complete bus cycle on every tick, compared with every 4 ticks on a real 68000.
Of course, this synchronisation requirement means that any accesses to the motherboard still take place on a 4 tick 7 MHz cycle. As with all accelerators, to actually realise the capability of the faster CPU a chunk of fast memory is needed. The DE0 Nano has a 32MB ISSI SDRAM on-board which is presented to the Amiga as a full 32MB in the Zorro 3 address space (we are not constrained by the 24-bit address bus of the real 68000). The presence of the fast memory really speeds things up, and you can see in the screenshots just how well the current prototype is working.
Reliability so far seems excellent, and I’m confident that there are still things to do that will make it run even faster.
As a further teaser here is the intro sequence from Frontier running silky smooth rather than the usual 2 or 3 fps you’d expect from an A500. You can watch this below…
Very cool Mike! I have a couple DE10 Nano boards as well here. If you need some help with building prototypes let me know. I would be happy to do some work here in the US for you. This is just what we all need to add some competition to the Vampire team. Even if its not as full featured as a Vampire it will still be what a lot of people want over the excessive cost of them now. If you open source this it would be even better.
I’ll put an order in now mate LOL
I’d love yo buy a complet kit someday. 🙂
Very nice! Is the ram-interface 32 bit or 16 bit wide? I have a simmilar project and struggeling to get a propper 32bit interface working with the tg68 core
16-bit currently because that’s all that was on the dev board. Because of that I haven’t spent much time on widening the bus, but TG68 looks to be quite tied to its internal 16 bit bus architecture, which I guess is what you’ve found.
Will it work in an A2000 as well?
Don’t see why not (size aside, and this will shrink dramatically).
I too would be interested in this.. I have a A500 rev6 and a A2000 – as a guess at a ballpark that one might sell for? Not to knock your project but there are quite a few now knocking on the sub 200Euro price and it because what do you get for what you are paying for. Love the project though Mike, all new approaches are fantastic to see.
@Paul Rezendes you can’t add any competition to Vampire team with this because TG68 core for Vampire 600 V1 was opensourced in 2013., as GPL requires. Also complete code for Amiga 500 regarding TG68 is something I have published on EAB. However I wasn’t first one who connected TG68 to some motherboard but original author of TG68, tobiflex, who posted his results on a1k, then also some others who tried posting their results on EAB. Porting those codes to nearly any FPGA is one hour job and basically is related to time spent for pin assignment.
@Mike good work but friendly reminder, if you are writting an article, dig deeper, history of TG68 and Amiga didn’t start like you showed here but much different.
Is this not more or less a clone / copy of the Vampire1 from Igor?
https://www.majsta.com/
@James Schofield Not sure how much it will cost yet. It will migrate to a different FPGA and cost will depend largely on the required size. At the moment I would say sub £200/€200 is doable.
@majsta This is not an article about the history of TG68. I’m fully aware of Vampire 1, and of TG’s earlier work, and as far as I’m aware the performance of this already surpasses both of those. I mentioned Minimig and particularly Mister only because they are being actively developed and have demonstrated a high level of compatibility with the real 68000.
Good work 🙂 this will be very compatiable, wich is what I want.
Wondering if you good make it CDTV compatiable? There is zero accelerators for a CDTV and it just happen to be pretiest Amiga ever. (and wife approved Amiga for a living room)
Lately Stephen Leary has made some work / digging for CDTV compatibility
https://github.com/terriblefire/cdtv.device
Short –>
cdtv.device blindly uses any ram its given for DMA memory. It doesnt check anything.
It also has spin loops and nops for delays which are terrible.
Its pretty limited compared to the cd32 cd.device
@Ismo: Sorry I never fully replied to this on EAB. I’m not familiar with the CDTV architecture other than it being fairly similar to the A500. Spin delay loops should be okay as long as they are executed from chipmem or the ROM (the motherboard interface is the same speed as the real 68000), but the DMA thing could be more of a problem to solve without a patched driver (which Stephen Leary’s work might solve anyway). It won’t be a priority but happy to give it some time later on in development.
From 2013 the TG68 received a lot of improvements and bug fix. On MiSTer it is nicely stable and fast like a 68030@66mhz. It is still not perfect ofcourse, but is actively developed and this is the most important thing.
wow that’s a lot of copper tape!
I’ve been wondering if something like this could be done, for the cpu and/or all the custom chips as things like CIA’s and whatnot are in such short supply.
But wow that Frontier II demo sequence was silky smooth! Great job!
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This is awesome , if you need software testing doing or youtube shout out let me know 🙂
So the speed range is a fast 68040? Currently…
@Gunnar – you seem to be incapable of distinguishing hardware designs. As for softcore – Igor adopted already open-source TG68 (by tobiflex) which was then further refined. This project is neither clone nor offshoot from Vampire v1 by Igor, and yes, Igor made real FPGA accelerator for Amiga and it was the first one around. That alone doesn’t make any other fpga accel clone of Vampire even if the same softcore is used. BTW V1 was based on Cyclone II custom designed board and this one is based on Cyclone IV development board (atm). Which already makes it totally different.
@majsta – Igor, this has nothing to with TG68 history. TG68 was and is used in FPGA-based retro emulators as a proven technology. That’s all the reason behind mentioning TG68 – because it obviously works and can be made faster with decent hardware. There is no history lesson, origins, anyone interested can check it by themselves how it was created, developed, maintained and used.
@Mike – As for the project – good luck. Market isn’t saturated solely by 030/50MHz turbo and Vampire V2. PPL have different needs and different budgets. Those who waited for rtg, sd, hdmi, fast ram and heavyweight cpu in one product probably already bought vampire. Those who doesn’t need all that but decent turbo+ram+ide might be interested with cheaper solution. And since FPGA can overtake 030/50MHz anytime it makes perfect sense. Because apollo team has no product to compete in that segment cheaper and less complex FPGA based turbo can reign it without much of a fight.
Are you Ready to take Preorders yet?
Not until I have a first batch back, which I’m hoping will be towards the end of the summer. After that, all being well, I would hope to go straight to shipping fairly quickly. At some point I might set up a “register your interest” page to gauge the size of production runs that will be required.
awesome
Hi Mike is there any update as to your card.
Still doing the PCB layout at the moment. It has been delayed by day job work unfortunately, but still progressing. I hope it will be on sale in time for Christmas, and possibly also a 1200 version.
awesome will the feature set be same for a1200 version or anything extra?
Hi Mike
Did you ever set up that ‘register your interest’ page? Would this product be portable to an A600? – or is that a consideration of yours?
Hi Mike,
Interesting project, great to see 🙂
Hopefully the MiSTer core can also see some performance gains from the work you are doing here 🙂
My MiSTer reports about 13 MIPS but it’s not quite fast enough, most games are fine but some could do with a slight boost.
Are you also going to release A1200 FPGA based accelerator?
For the A500 with just OCS/ECS, I can suggest the following ‘power’ games to try out with your board:
http://aminet.net/package/game/shoot/AmiWolf_ECS
http://aminet.net/package/game/shoot/AmiSpear_ECS
http://aminet.net/package/game/misc/ScummVM_ECS_030
All of these titles should run on an accelerated A500.
🙂
Given the delays in getting the hardware out, which are just due to my current day job workload, yes my intention is to try to get an A1200 version out pretty much at the same time. I would expect that to be a fair bit faster due to the 32-bit bus.
Thanks for the tips on the games for testing.
I think you can expect question about A600 variant as well 🙂
any updates?
Yes. The layout is done but the 8 layer board means there is a lot of upfront cost, so I haven’t pressed the button on a manufacturing run yet, and I need to get some day-job stuff out of the way anyway. I am also pressing ahead with an A1200 version which will be a lower layer count and therefore cheaper tooling.
if you need minmium preorder number let us all know, i’m sure there be quite a few interested in this? for a500 and a1200 maybe a2000 too
Hi Mike,
The MiSTer FPGA project might be able to benefit from your TG68K improvements, do you have a link to your source repository with the updates?
The MiSTer team have suggested that you store you updates/fixes in this repository:
https://github.com/TobiFlex/TG68K.C
Thanks mate 🙂
Hi Mike,
I’ve been following for a while now with interest.
Maybe if cost is an issue you could setup on a crowd funding website with those who support the amount needed for each board getting theirs when it is ready. I would be very much interested in the a1200 version, I also have a MiSTer fpga board which would be amazing if you could collaborate with that to help, it’s an amazing device and project.
Any updates?
Brilliant stuff.. Any plans for the ‘free’ arm cpu in the fpga or will you be down sizing the fpga eventually?
Ok, scratch that, just caught up on the EAB thread, sorry
There is no ARM CPU in this FPGA anyway – you’re thinking of the Zynq (or the Cyclone SoC).
Hi Mike
It looks like you have done some great work improving the already excellent TG68k, perhaps we can talk about sponsoring your changes back into Github.
I would also be interested in supporting any FPU work you may be able to do.
Steve