The Amiga is still a popular platform with enthusiasts, with the vibrant add-on scene still seeing new accelerator cards being developed. Most of these are based on the long obsolete faster derivatives of the 68000, such as the 68030 and 68060. These are getting increasingly hard to find for a reasonable price.
For the last few weeks I’ve been tinkering with hooking an FPGA up to an A500+ in place of its 68000 CPU with a view to using the open-source TG68 core as a fast 68020. This core is already proven in projects such as Minimig and MISTer, so it seemed like a logical choice. Rather than going straight to a custom PCB I made the decision to use an existing FPGA development board that I had on hand, along with a simple level shifting interface put together on stripboard. This has proved to work perfectly well for testing, although the grounding did need to be beefed up with copper tape to get things working reliably. A proper PCB with an FPGA integrated will be designed in due course.
The FPGA board itself is a Terasic DE0 Nano, for no particular reason other than I had a spare one. This features an Intel Cyclone IV FPGA as well as 32MB of SDRAM and a few other peripherals that aren’t of much interest here.
The TG68 does not have a regular 68000 interface, nor does it implement a real 68000 bus cycle. The Amiga is extremely sensitive to the timing of the motherboard bus cycle due to the way that Agnus handles its DMA cycles to chip memory. Getting the motherboard bridge logic properly synchronised was one of the hardest aspects of the design so far. To make it work reliably the accelerator needs to run at an even multiple of the motherboard clock – 42.6MHz currently. This may not seem like a huge step up, but TG68 typically executes a complete bus cycle on every tick, compared with every 4 ticks on a real 68000.
Of course, this synchronisation requirement means that any accesses to the motherboard still take place on a 4 tick 7 MHz cycle. As with all accelerators, to actually realise the capability of the faster CPU a chunk of fast memory is needed. The DE0 Nano has a 32MB ISSI SDRAM on-board which is presented to the Amiga as a full 32MB in the Zorro 3 address space (we are not constrained by the 24-bit address bus of the real 68000). The presence of the fast memory really speeds things up, and you can see in the screenshots just how well the current prototype is working.
Reliability so far seems excellent, and I’m confident that there are still things to do that will make it run even faster.
As a further teaser here is the intro sequence from Frontier running silky smooth rather than the usual 2 or 3 fps you’d expect from an A500. You can watch this below…