BBC Micro on FPGA


Chuckie Egg running on BBC FPGA

Chuckie Egg running on BBC FPGA

Following on from the Sinclair Spectrum, the other machine I got to play with a lot as a kid was the Acorn BBC Micro.  In mid-to-late 80s UK there were several of these in every primary school (unless mine was unusually affluent). Secondary schools had them by the roomful at least until the mid-nineties, when they were finally supplanted by the might of the PC.

For many of my generation this was probably their first experience of computing without the agonising wait for programs to load from tape; the Beeb of course supported a tape interface, but most were installed with a 5 1/4” (very) floppy disk drive. Graphically, the ubiquitous Microvitec Cub monitor was a big step up from the usual re-purposed TV.

There were several versions of the BBC, each in a similarly styled beige box with integral keyboard. The originals, Models A and B, were pretty similar with the A having half as much memory. The Model A could be upgraded later to match the Model B specification, but the B proved more popular anyway. Later came the memory-enhanced Model B+, with subsequent revisions becoming the Master series. The most obvious additions in the Masters were the cartridge slots and numeric keypad, as well as even more RAM.

With fond memories of educational titles like “Granny’s Garden”, and less educational ones like “Pole Position” and “Boffin”, the BBC B seemed like a worthy machine to bring back to life inside an FPGA.


The heart of the BBC was the popular 6502 processor, variants of which were also found in machines by Atari, Commodore and Apple, among many others. A summary of the architecture for the model B is as follows, along with the current status of each item in the FPGA design:

  • DONE – CPU: MOS 6502 running at 2 MHz, except when accessing certain peripherals when the clock would be automatically reduced to 1 MHz.
  • DONE – RAM: 32KB DRAM running at 4 MHz, time-sliced with and refreshed by the video hardware (no contention!).
  • DONE – ROM: 16KB MOS ROM, 4x 16KB paged ROM slots. One of the paged ROM slots is taken up by the BASIC interpreter, with another usually filled with the Disk Filing System (DFS). Third party expansions allow more than 4 ROMs to be fitted.
  • DONE – Bitmapped display: Motorola MC6845 CRT Controller + custom Ferranti Video ULA (VIDPROC). The 6845 provides addresses to the DRAM, and additional address-wrap logic means that hardware scrolling can be achieved without the display running beyond the end of the video RAM.
  • MOSTLY – Teletext mode (MODE 7): Mullard SAA5050 character generator.
  • DONE – Sound: Texas Instruments SN76489 accessed via the System VIA.
  • DONE – IO: Two 6522 VIA chips provide a pair of 8-bit GPIO ports each, timers and interrupt inputs. The System VIA provides indirect access to the keyboard and various other hardware over a “slow bus”. One of its timers is used for a 10 ms OS tick, and the four external interrupts are used by the keyboard, vertical sync, ADC and light pen interface. The user VIA drives the printer and user ports, the latter directly.
  • NOT IMPLEMENTED – Serial: 6850 UART and another Ferranti ULA (SERPROC) provide an RS-423 serial port and a “Kansas City” tape interface.
  • NOT IMPLEMENTED – Disk Interface: In the earlier machines an Intel 8271 floppy disk controller provides an interface for a pair of double-sided drives.
  • NOT IMPLEMENTED – Network: Acorn’s own “Econet” is catered for by a Motorola 68B54 Advanced Data Link Controller IC. Like the disk interface this was an optional extra and also requires the addition of the NFS ROM.
  • NOT IMPLEMENTED – ADC: Four multiplexed analogue inputs, useful for joysticks and instrumentation, are provided by a uPD7002 12-bit ADC.
  • Buses: Two expansion buses are exposed on the underside of the machine. The 1 MHz bus was used by peripherals such as the teletext interface, whilst the Tube port is a co-processor bridge. No attempt has been made to make these buses available to the outside world. However, simulating them on the expansion headers should take very little effort.

FPGA Implementation

BBC FPGA on Terasic DE1

BBC FPGA on Terasic DE1

The project was, like the Spectrum, implemented on a Terasic DE1 board with an Altera Cyclone II FPGA. The entire design is written in VHDL, and it fits in 2907 logic elements when compiled on Quartus 9.1. This is about 16% of the capacity of the EP2C20. A small amount of on-chip memory is used for the teletext character generator ROM, with the program ROMs residing in off-chip flash.

At this stage no attempt has been made to add a scan-doubler for the video output, so a PAL TV is required for display. A SCART lead can be made to connect to the VGA port on the DE1; the HSYNC pin generates PAL compatible CSYNC, and the VSYNC pin is driven to +5 V. The latter should be connected to pin 16 of the SCART plug to make the TV go into RGB mode.

Sound is available on the green line-out connector and this can be fed into the SCART lead as well if desired, or to separate speakers.

A PC PS/2 keyboard is required (here is the keymap, click for larger).

Key map for FPGA BBC using a PC keyboard

Key map for FPGA BBC using a PC keyboard

Download the .sof file to run on your own DE1. For normal operation switches 8 and 9 should be in the up position, the rest down. Switch 9 is system reset, switch 8 is the run/stop input to the hardware debugger (more on this later). The remaining switches appear as the keyboard DIP switches, most of which are unused, but the lower three control the startup MODE.


I am not providing the ROM images for download here as I am not sure of their legal status and they are not hard to find elsewhere anyway. The following ROMs are required:

  • os12.rom
  • basic2.rom
  • supermmc.rom

The MMC ROM is part of MMBEEB and provides access to disk images on an SD card.

The three ROM images must be concatenated and loaded into the bottom of the DE1’s flash using the tool that came with the board. I joined the ROMs on Linux just by doing:

$ cat os12.rom basic2.rom supermmc.rom >all.rom


Note that the ROM order is important, and at the very least the MOS ROM must come first.

UPDATED:  The latest version of this project now includes some addressing changes to allow the BBC ROM images to coexist with those from the Spectrum.  8x 16 KB banks are reserved in the DE1’s Flash address space for use by the BBC, and the relevant ROM images must be loaded first using the tools that came with the DE1 board.

  • 0x20000 – Sideways ROM
  • 0x24000 – Sideways ROM
  • 0x28000 – Sideways ROM (load with SUPERMMC)
  • 0x2C000 – Sideways ROM (load with BASIC)
  • 0x30000 – Not used
  • 0x34000 – Not used
  • 0x38000 – Not used
  • 0x3C000 – MOS

Known Issues

The MODE 7 teletext support does not implement the “hold graphics” feature, which may corrupt some displays. Character rounding is not implemented either, which doesn’t matter so much.

Occasionally the machine will hang, usually at the same point in certain programs. I haven’t spent much time tracking this one down but it appears to be something to do with interrupt handling, so it could be a CPU bug. Manic Miner, for example, starts with an animated graphic like on the Spectrum. On the BBC this uses a vertical sync event handler and so runs in interrupt context. On the FPGA the animation and scrolling ticker run too fast and at irregular pace, and the game can’t be started.

Some of the unimplemented features would be nice to have. In particular the serial hardware for the tape interface, and the floppy disk controller to enable a real drive to be attached. I plan to add these in due course.


The following blocks are used in the design. Modifications were required in some cases – details on the design page.


Update 2016-01-13: The files are now also available on GitHub

51 thoughts on “BBC Micro on FPGA



    Great work, it is all beyond me!
    I tired the core on both the ZX-Uno & MiST and the game ‘Castle Quest’ (my fav game from school!) does not work 🙁
    Most of the BEEB.MMB images on the net have a Compilation version which crashes out to ‘Error on Line 40’, but I also tried about 4 other versions of just Castle Quest. These load, there are some graphical errors on the title screen, looks like flames at the bottom of the ‘Castle Quest’ logo? And when you get into the game only the background shows?

    Any chance the core could be looked at please?


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